The fetch-decode-execute cycle

Overview

Recall questions on the fetch, decode and execute stages, how each register changes during a store, add or jump instruction, conditional and unconditional jumps, which bus carries the instruction, and why the program counter is incremented during the fetch.

What you need to know

Answer each one before you reveal it.

Questions from this subtopic

Each one with the model answer underneath.

1. 1

   Give the fetch stage step by step, saying what each register holds as you go.

   Model answer

   1. The address in the program counter is copied into the MAR. 2. The program counter is incremented by one, so it now holds the address of the following instruction. 3. The address in the MAR is placed on the address bus and the control unit sends a read signal on the control bus. 4. The instruction stored at that address travels back along the data bus into the MDR. 5. The contents of the MDR are copied into the CIR. At the end of the fetch: the PC holds the next instruction's address, the MAR holds the address just read from, the MDR holds a copy of the fetched instruction, and the CIR holds the instruction about to be decoded.

2. 2

   What happens during the decode stage?

   Model answer

   The control unit examines the instruction sitting in the CIR and splits it into its opcode and its operand. From the opcode it determines which operation is required, how the operand should be interpreted, and which components and control signals will be needed. No memory access takes place and no other register changes; the instruction stays in the CIR throughout decode and execute.

3. 3

   Walk through the execute stage for an instruction that adds the contents of a memory location to the accumulator.

   Model answer

   The operand, which is the address of the value to add, is copied from the CIR into the MAR. The address goes out on the address bus with a read signal on the control bus, and the value at that location returns on the data bus into the MDR. The ALU adds the contents of the MDR to the current contents of the accumulator, and the result is written back into the accumulator. The program counter already holds the next address, so the cycle begins again.

4. 4

   Trace the registers for an instruction that stores the accumulator into memory location 40.

   Model answer

   The CIR holds the store instruction with operand 40. During execute, 40 is copied from the CIR into the MAR and the contents of the accumulator are copied into the MDR. The control unit sends a write signal on the control bus; the address bus carries 40 and the data bus carries the contents of the MDR, and the value is written into location 40. The accumulator itself is unchanged, and the program counter still holds the address of the next instruction.

5. 5

   Why is the program counter incremented during the fetch rather than at the very end of the cycle?

   Model answer

   Because the execute stage may need to write a new address into the program counter. If the increment happened last it would overwrite the target of a jump. Incrementing early means the program counter is already correct for ordinary sequential flow, and a jump simply replaces that value during execute. It also means the address of the next instruction is ready the moment the fetch finishes, which is what allows the next fetch to be overlapped.

6. 6

   What happens differently in the registers when the instruction is an unconditional jump?

   Model answer

   Everything up to decode is the same. During execute, instead of using the ALU or memory, the operand from the CIR, which is the target address, is copied into the program counter, discarding the incremented value put there during the fetch. The next fetch therefore copies the target address into the MAR and execution continues from there. Writing to the program counter is the only way the flow of a program leaves its sequential order.

Other ways to work this

The same content, four other ways.

What is inside Levo

Six ways to work the same material.